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Actel Libero IDE SP1 8.6.2.10

20 Feb, 2010  Design, Windows

Actel Libero IDE SP1 8.6.2.10
Software for design and design of all models of families of Actel FPGA.
The software product is optimized to take advantage of features of the architecture designed devices, including the unique on-chip flash ROM (FlashROM), which can easily be programmed independently of the core FPGA.

Developer Kit Libero supports input design data in a mixed mode, so that developers have a choice: to use the draft schematic modules in conjunction with high-level language such as blocks or VHDL, or Verilog HDL.
In the new version prgrammnogo complex, Actel Corporation (NASDAQ: ACTL) continues to pave the way for the successful development of structures with low energy consumption.

Libero IDE Software Features:
Powerful project and design flow management
Full suite of integrated design entry tools and methodologies:
SmartDesign graphical SoC design creation with automatic abstraction to HDL
Core Catalog and Configuration
HDL and HDL templates
“User-defined block” creation flow for design re-use
ViewDraw Schematic Capture
Actel cell libraries
Synplify/Synplify Pro AE synthesis fully optimizes Actel FPGA device performance and area utilization
Synplify DSP AE performs high-level DSP optimizations within a Simulink environment
ModelSim VHDL or Verilog behavioral, post-synthesis and post-layout simulation capability
Designer physical design implementation, floorplanning, physical constraints, and layout
Timing- and power-driven place-and-route
SmartTime environment for timing constraint management and analysis
SmartPower provides comprehensive power analysis for actual and “what if” power scenarios
Interface to FlashPro and Silicon Sculptor programming software
Post-route probe insertion and Identify AE debugging software for Actel flash designs
Silicon Explorer debugging software for Actel antifuse designs
Supported on Windows and Linux operating systems

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